Lead-on-chip (LOC) is a packaging technique employed by several semiconductor manufacturers, particularly those whose make semiconductor memory devices, including DRAMs (dynamic random access memories) and SRAMs (static random access memories). Conventional LOC devices have a plurality of leads which are disposed on and attached to an active surface of a semiconductor chip, thus the name lead-on-chip. A primary advantage of LOC is that the ratio between the size of the semiconductor chip and the size of a package which encapsulates that chip is quite high. This advantage is achieved because a chip mounting area, also known as a flag or a die pad, is not required since the chip is instead attached to the leads. The chip size to package size ratio is an important factor to semiconductor manufacturers because customers continue to demand smaller and smaller devices.
While LOC is an attractive packaging alternative in some regards, many proposed LOC schemes are not flexible enough to accommodate various chip designs. For instance, much of the existing LOC technology requires bond pads of a semiconductor chip to be located in a central row of the chip. Several semiconductor manufacturers, however, have existing chip designs which have peripheral bond pads. Other LOC techniques have been developed for chips with bond pads on two opposing end of a chip. Nonetheless, these techniques are not applicable to chips have bond pads distributed around the entire periphery of the chip. In order to benefit from the advantages of LOC, semiconductor manufacturers must re-design the peripheral bond pad chips to have end-only bond pads or centrally located bond pads. Chip re-designs are costly and time-consuming. Furthermore, redesigning the chip may result in a chip which is larger than the originally designed chip. As another example, some semiconductor manufacturers design a chip so that the chip can be packaged using any one of several techniques rather than having to re-design the chip for each type of package. A common case is a chip which is designed to be packaged using either a metal leadframe or a TAB (tape automated bonding) leadframe. Much of the existing LOC technology is directed solely to the use of metal leadframes and cannot be implemented in TAB.